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ZEN2011P
P ROGRAMMABLE UNIVE RSAL COUNTE R
Description ZENIC INC. ZEN2011P is a 24 bit pr ogr a m m a ble u n iver sa l cou n t er LSI. TH E ZEN2011P cou n t s ph a se-sh ift ed sign a ls a n d u p/down pu lse sign a ls, gen er a t ed fr om r ot a r y en coder s or lin ea r sca les. Sin ce t h e cou n t er r espon se speed is a s h igh a s 8MH z(MAX),t h e ZEN2011P is u sed in a va r iet y of h igh speed ser vices in clu din g digit a l ser vo con t r ol a n d pr ecision m ea su r em en t . TH E ZEN2011P is pr ovided wit h a fu n ct ion wh ich m on it or s in pu t sign a ls a n d det ect s a n y a bn or m a l in pu t a ccom pa n ied wit h n oise or ot h er dist u r ba n ces, so t h a t t h e r elia bilit y of cou n t ed va lu es a r e secu r ed.
1, Features 24bit bin a r y u p/down cou n t er . Cou n t er r espon se speed: 8MH z.(MAX) ( CLK f0 = 8MH z a t 50% du t y) In pu t fr equ en cy of cou n t pu lse. Two ph a se-sh ift ed pu lses sign a l in pu t : A/B ph a se in pu t DC ~ 2MH z. (less t h a n f0 ~ 1/4) U p/down pu lse sign a l in pu t : U p/down in pu t DC ~ 4MH z (less t h a n f0 ~ 1/2) CLK fr equ en cy DC ~ 8MH z. (MAX.: du t y r a t io 50%) Dir ect ion r ecogn it ion for u p/down cou n t Abn or m a l in pu t det ect ion cir cu it . P r eloa d r egist er for t h e u p/down cou n t er . La t ch r egist er for t h e u p/down cou n t er . Refer en ce va lu e - cou n t va lu e coin ciden ce det ect ion fu n ct ion . On -ch ip st a t u s r egist er . Cou n t er oper a t ion m ode. Qu a d/dou ble/sin gle edge eva lu a t ion . (for ph a se-sh ift ed sign a l a n d sin gle pu lse) Cou n t dir ect ion select ion . Cou n t er clea r con t r ol:syn ch r on ou s/ a syn ch r on ou s clea r . Com m a n d m ode Mode 0: 1 ch . r efer en ce va lu e - cou n t va lu e coin ciden ce det ect ion fu n ct ion . Mode 1: Mode 0 in st r u ct ion set com pa t ible. 2 ch . r efer en ce va lu e - cou n t va lu e coin ciden ce det ect ion fu n ct ion . Logica l OR ou t pu t of ea ch coin ciden ce det ect ion s a va ila ble. In t er r u pt ou t pu t u n der som e con dit ion s a va ila ble.
8 bit da t a bu s. Low power CMOS t ech n ology. TTL com pa t ible. Sin gle 5V power su pply. 28 pin DIP . Typical Applications N C m a ch in e t ools P r ecision posit ion er s Robot a r m con t r oller s Speed con t r oller s for r ot a t in g m a ch in es E lect r on ic ga u ges F r equ en cy cou n t er s
Pin configuration (Top View) E XTA CLK RE SE T CE C/D RD WR LD LT D0 D1 D2 D3 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDD U D/AB DIR SE L0 SE L1 SE L2 A/U P B/DN Z/CLR E XTB D7 D6 D5 D4
ZEN2 0 1 1 P
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ZEN2011P
2, Block diagram
* Mode 1 LT LD C/D WR RD CE
Com m a n d r egist er
E XTA E XTB
Com m a n d decoder
(8bit ) Mode 0
Com m a n d r egist er
(8bit ) * St a t u s r egist er (8bit ) Mode 1 F u n ct ion con t r ol E QA Refer en ce r eg. A (24bit ) E QB
Com pa r a t or A (24bit ) * Refer en ce r eg. B (24bit ) * Com pa r a t or B (24bit )
La t ch r egist er (24bit ) RE SE T SE L0 ~ SE L2 U D/AB DIR AI A/U P B/DN Z/CLR CLK Dir ect ion r ecogn it ion for u p/down
U P P U LSE DOWN P U LSE COUN TE R CLE AR
U p/down cou n t er (24bit )
P r eloa d r egist er (24bit )
VDD VSS D7~D0 N ot e:Block s m a r k ed(*) a r e va lid a t m ode -1
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ZEN2011P
3, Pin Description (1) E XTA E xt er n a l A(Ou t pu t ) Th is ou t pu t depen ds on t h e com m a n d m ode. In m ode 0, E XTA ou t pu t s t h e equ a l sign a l (E QA). In Mode 1, eit h er of da t a (E QA), (E QA+E QB) or (IN TE QA) is select ed by t h e com m a n d a n d it is ou t pu t . Refer t o "5-3 Mode 1 com m a n d for m a t ". (2) CLK Clock (In pu t :sin gle ph a se clock) Th e CLK ser ves a s a clock in pu t solely t o syn ch r on ize t h e in t er n a l cir cu it oper a t ion of t h e ZEN2011P. (3) RE SE T Reset (In pu t ) Th e RE SE T in it ia lizes t h e u p/down cou n t er , ph a se discr im in a t ion cir cu it , com m a n d r egist er ,a n d st a t u s r egist er . (4) CE Ch ip en a ble(In pu t ) A "Low" level a t t h is in pu t en a bles t h e ZEN2011P t o a ccept a com m a n d or a da t a in pu t fr om t h e CP U du r in g a wr it e cycle, or t o t r a n sm it a da t a t o t h e CP U du r in g a r ea d cycle. (5) C/D Com m a n d/da t a select (In pu t ) Th e C/D defin es t h e t ype of in for m a t ion t r a n sfer per for m ed bet ween t h e CP U a n d t h e ZEN2011P. (6) RD Rea d st r obin g(In pu t ) Th e RD is a st r obin g sign a l for r ea din g da t a fr om a n in t er n a l r egist er . (7) WR Wr it e st r obin g(In pu t ) Th e WR is a st r obin g sign a l for wr it in g da t a in t o a n in t er n a l r egist er . (8) LD Da t a loa din g t o t h e cou n t er *(In pu t ) Th e LD collect ively t r a n sm it s t h e da t a st or ed in t h e pr eloa d r egist er t o t h e u p/down cou n t er . (9) LT Cou n t da t a la t ch *(In pu t ) Th e LT collect ively st or es t h e da t a of t h e u p/down cou n t er in t o t h e r ea din g r egist er . (10~13,15~18) D0~ Da t a bu s(Bidir ect ion a l 3-st a t e) D7 (19) E XTB E xt er n a l B (I/O) Th e da t a set depen din g on t h e com m a n d is in pu t or ou t pu t . In m ode 0, E XTB is set a s u n iva r sa l in pu t t er m in a l U a n d it is m on it or ed by t h e st a t u s r egist er . In Mode 1, E XTB is set a s a n ou t pu t t er m in a l, eit h er of da t a (E QB), (INTAI) or (IN TE QB) is select ed by t h e com m a n d a n d it is ou t pu t . Refer t o "5-3. Mode 1 com m a n d for m a t ". (20) Z/CLR Cou n t er clea r *(In pu t ) Th e Z/CLR a ccept s r eset sign a l wh ich clea r s t h e u p/down cou n t er da t a . (21) B/DN Cou n t pu lse in pu t B or DN *(In pu t ) (22) A/U P Cou n t pu lse in pu t A or U P *(In pu t ) Th e B/DN a n d A/UP a ccept s cou n t pu lse sign a ls for t h e 24 bit cou n t er . (23~25) SE L0~SE L2 Cou n t er m ode select (In pu t ) Th e con dit ion s of t h ese pin s defin e t h e cou n t er oper a t ion m ode t o sin gle ph a se or t o du a l ph a se. Th is defin it ion is effect ive wh en U D/AB ="Low". (26) DIR Cou n t er dir ect ion select (In pu t ) Th e DIR select s t h e cou n t dir ect ion of t h e u p/down cou n t er . (27) U D/AB U p/down or du a l ph a se pu lse m ode select (In pu t ) P lea se r efer t o t h e pa r a gr a ph of "4-3. Select ion of cou n t er oper a t ion m ode". (14) VSS Gr ou n d(0v) (28) VDD Su pply volt a ge(+5v) N ot e: Sign a ls wit h (*)m a r k a r e sa m pled by CLK. Sa m pled a t t h e r isin g edge of CLK: Z/CLR,B/DN ,A/U P Sa m pled a t t h e fa ilin g edge of CLK: LD,LT.
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ZEN2011P
4, Operation Th e oper a t ion of ZEN2011P is con t r olled wit h t h e syst em soft wa r e. To u se t h is cou n t er , it is n ecessa r y t o specify "com m a n d wor ds", "cou n t er r efer en ce va lu e",a n d "cou n t ed va lu e" in a dva n ce. Sin ce t h e t im in g is syn ch r on ized wh ich t r a n sfer da t a bet ween t h e u p/down cou n t er a n d ot h er r egist er s, t h e da t a r ea d/wr it e, com m a n d wr it e, a n d st a t u s r ea d ca n be ca r r ied ou t even wh en t h e cou n t er is oper a t in g. 4-1.Command mode L In ZEN2011P, t wo k in ds of syst em m ode descr ibed in t h e followin g ca n be select ed. F ir st of a ll, it is n ecessa r y t o select eit h er of syst em m ode by t h e com m a n d in in it ia liza t ion . N ext , it is n ecessa r y t o specify a com m a n d wor d, a cou n t er va lu e, a n d a va lu e of ea ch r egist er n ecessa r y for in it ia lizin g t h e cou n t oper a t ion befor eh a n d. (1) Mode 0 ( Aft er com m a n d:90H is execu t ed or syst em r eset ) E XTB (pin N o.19) is set a s u n iver sa l in pu t t er m in a l U. Th e r efer en ce r egist er -A a n d t h e com pa r a t or -A becom e effect ive. (2) Mode 1 ( Aft er com m a n d:91H is execu t ed ) In t h is m ode it is a va ila ble a s for a ll in st r u ct ion set s of m ode 0. E XTB (pin N o.19) is set in t h e ou t pu t t er m in a l. Mor eover , E XTA (pin N o.1) a n d E XTB (pin N o.19) ca n con t r ol t h e ou t pu t da t a by t h e in st r u ct ion set of Mode 1. Mor eover , t h e r efer en ce r egist er -B a n d t h e com pa r a t or -B becom e effect ive. L H H L H H St a t u s r ea d(st a t u s r egist er ) L Com m a n d wr it e(com m a n d r egist er ) Tab.1 The read/write operation CE C/D RD WR H X X Oper a t ion
X Disa ble(da t a bu s is a t h igh im peda n ce con dit ion ) H Da t a r ea d(la t ch r egist er ) L Da t a wr it e(pr eloa d,r efer en ce r egist er , u p/down cou n t er )
L L
L L
L H
4-3.Selection of counter operation mode Th e ZEN2011P sa m ples t h e cou n t in pu t s u sin g t h e CLK. U sin g fou r sign a ls of U D/AB a n d SE L0 ~ SE L2, t h e t ype of cou n t er pu lse in pu t a n d t h e t ype of cou n t er clea r ca n be select ed. Refer t o Ta b.2 for det a il. Th e cou n t in g oper a t ion s a r e ca r r ied ou t by sa m plin g t h e con dit ion s of A,B,a n d Z a t t h e r isin g edge of CLK.
4-2.Read/write logic Th e r ea d or wr it e oper a t ion of t h e ZEN2011P is select ed u sin g fou r sign a ls, CE , C/D, RD, a n d WR. Det a il of t h e select ion is sh own in Ta b.1.
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Tab.2 Counting mode selection
UD/AB SE L2 SE L1 SE L0
4-4.Count operation with pulse input Clea r m ode Asyn ch r on ou s clea r
P u lse in pu t (E dge eva l.) U p/Down pu lse
P u lse U p/down pu lse
Cou n t oper a t ion
H
X
X
X
At t h e r isin g U P ,DN pu lse. At t h e ph a se ch a n ge of A,B pu lse Sin gle:Ch a n ge of ph a se A (on ly wh en ph a se B is "L") Dou ble:Ch a n ge of ph a se A Qu a d :Ch a n ge of ph a se A,B
L
L
L
P h a sesh ift ed (Sin gle) P h a sesh ift ed (Dou ble) P h a sesh ift ed (Qu a d) P h a sesh ift ed (Sin gle) P h a sesh ift ed (Dou ble) P h a sesh ift ed (Qu a d) Sin gle pu lse Asyn ch r on ou s clea r m ode Syn ch r o -n ou s clea r m ode
P h a sesh ift ed
L
L
H
L
H
L
Cou n t u p wit h pu lse A, a s cou n t Sin gle en a ble sign a l wit h B. pu lse Sin gle:Ch a n ge of ph a se A (on ly a t t h e r isin g pu lse) Dou ble:Ch a n ge of ph a se A
Edge evaluation ( 1:count 0:not count ) Up/down pulse input UP DN 1 1 1 1 N ot e: Bot h u p/down pu lse sh ou ld n ot be sim u lt a n eou sly set t o a "Low" level. Phase-shifted pulse input A
H L H
L
L
L
H
H
H
L
L
H
H (Sin gle)
B Sin gle pu lse H H H (Dou ble) Sin gle 1 Dou ble 1 Qu a d 1 0 0 1 0 1 1 0 0 1 0 0 1 0 1 1 0 0 1 1 1 1
Single pulse input A B Sin gle 1 0 1 0 0 0 0 0 Dou ble 1 1 1 1 0 0 0 0 N ot e: B is u sed for a cou n t en a ble sign a l.
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4-5.Detection of abnormal input 4-6.Internal register conditions Th e ZEN2011P h a s a fu n ct ion t o ch eck wh et h er t h e ph a se-sh ift ed in pu t pu lse in pu t sh ow a cor r ect t r a n sit ion st a t e (sh own in F ig.1 wit h m a r k s) or n ot . Wh en a n a bn or m a l t r a n sit ion st a t e (sh own in F ig.1 wit h m a r k s) occu r s,D7 of t h e st a t u s r egist er t o "H " wh ich m ea n s t h e a bn or m a l in pu t fla g(AI). Som e of a bn or m a l t r a n sit ion st a t e a r e a s follows: (1)Th e fr equ en cies of ph a se-sh ift ed pu lse in pu t s exceed t h e on e fou r t h of t h e syst em clock fr equ en cy, so CLK ca n n ot sa m ple t h e t r a n sit ion st a t e cor r ect ly. (2)Th e lin e-n oises a r e sa m pled, so t h a t ZEN2011P det ect s a n a bn or m a l t r a n sit ion . Phase-shifted pulse input Refer en ce r eg. AB 11 A 0 11 00 11 0 01 00 Fig.1 Example of transition state 10 B 00 11 00 11 Com m a n d r egist er D7 (LD) D6 (ZE 1) D5 (ZE 0) D4 (LT) D3 (RS1) D2 (RS0) D1 (BS1) D0 (BS0) St a t u s D7 D6 D5 D4 D3 D2 D1 D0 r egist er (AI) (Z) (A) (B) (DTR) (U /D) (E QA) (U ) 0 0 1 0 0 0 0 0 (N OP ) ZN E m ode (N OP ) Low byt e of t h e u p/down cou n t er a n d t h e r ea din g r egist er a r e select ed. La t ch r egist er " P r eloa d r egist er " " Aft er t h e syst em r eset , t h e defa u lt va lu es of t h e in t er n a l r egist er s a n d t h e syst em m ode a r e defin ed Ta b.3. Th e syst em r eset is don e, by a pplyin g a "Low" level pu lse t o RE SE T. Tab.3 Internal register condition
Regist er , m ode Cou n t er P r eloa d r egist er
Syst em r eset 000000H t h e va lu e ju st befor e t h e r eset t in g
0 Det er m in ed by in pu t " " 0 Det er m in ed by in pu t 1 Det er m in ed by in pu t m ode 0
(Z) (A) (B) (A,B) (U )
Syst em m ode
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5,Command register Th is is a r egist er wh ich st or es t h e "com m a n d wor ds" t o con t r ol t h e ZEN2011P. Th e com m a n d wor ds a r e en t er ed t h r ou gh a da t a bu s a n d a r e st or ed in t o t h e com m a n d r egist er . Th e com m a n d wor ds h a ve t wo kin ds of t h e in st r u ct ion set of Mode 0 a n d Mode 1. Th e in st r u ct ion set of Mode 1 ca n n ot be execu t ed a t Mode 0 oper a t ion s. H owever , a ll in st r u ct ion set s a r e execu t a ble a t Mode 1 oper a t ion s. Th is specifica t ion does n ot n eed t o be en t er ed for e v e r y b y t e , b e ca u s e t h e s p e ci fi e d p os i t i on a u t om a t ica lly m oves. LT(La t ch ) Th is com m a n d is u sed t o st or e t h e cou n t ed da t a of t h e u p/down cou n t er in t o t h e r ea din g r egist er . ZE 0,ZE 1(Z ph a se con t r ol) Th e Z ph a se in pu t sign a ls a r e u sed a s a clea r sign a l for t h e u p/down cou n t er . ZE 0 a n d ZE 1 set t h e effect ive n u m ber of clea r pu lses. LD(Loa d) Th is com m a n d is u sed t o t r a n sm it t h e da t a wh ich a r e st or ed in t h e pr eloa d r egist er t o t h e u p/down cou n t er .
5-1. System mode set command It is t h e com m a n d wor d t o select syst em m ode. It is n ecessa r y t o select eit h er of m ode. Format of the command register(system mode)
D7 D6 D5 D4 D3 D2 D1 D0 H ex
Oper a t ion Mode 0 select Mode 1 select
N ot e 1) In t h e Loa d a n d La t ch oper a t ion s, do n ot execu t e LD a n d LT sim u lt a n eou sly eit h er by soft wa r e com m a n ds or by ext er n a l pin s. N ot e 2) To execu t e a LT com m a n d or a LD com m a n d , it is n ecessa r y t o fix t h e ext er n a l pin s, LT a n d LD, a t a "H " level. field format of command register(mode 0)
1 1
0 0
0 0
1 1
0 0
0 0
0 0
0 1
90 91
(1) Mode 0 ( defa u lt ) D7 As for E XTA (pin N o.1), com pa r a t or ou t pu t E QA is ou t pu t . Mor eover , E XTB (pin No.19) becom es a n in pu t m ode a n d is set in u n iver sa l in pu t U . (2) Mode 1 E XTB (pin N o.19) becom es a n ou t pu t m ode a n d ca n set ou t pu t da t a wit h E XTA (pin N o.1) depen din g on t h e com m a n d of Mode 1. 5-2. Mode 0 : Functions and formats of the command register BS0,BS1(Byt e select ) Sin ce t h e t h r ee r egist er s(pr eloa d,r efer en ce, a n d la t ch ) a n d u p/down cou n t er h a ve 24 bit len gt h , Th e BS0 a n d BS1 divide t h e 24 bit in t o h igh byt e, m iddle byt e, a n d low byt e, ea ch of wh ich h a s 8 bit , a n d specify t h e byt e t o be a ccessed. RS0,RS1(Regist er select ) Th e RS0 a n d RS1 specify a r egist er t o be a ccessed a m on g t h e t h r ee r egist er s(pr eloa d, r efer en ce a n d la t ch ) a n d up/down counter. ZENIC Inc. -7D6 D5 D4 D3 D2 D1 D0
LD ZE 1 ZE 0
LT RS1 RS0 BS1 BS0
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ZEN2011P
Format of the command register(mode 0)
D7 D6 D5 D4 D3 D2 D1 D0
Oper a t ion (defa u lt )
x x x x x x x x x x x x 0 0 1 1 1
x x x x x x x x 0 0 1 1 x x x 0 x
x x x x x x x x 0 1 0 1 x x x 0 x
x x x x x x x x x x x x 0 1 0 1 1
0 0 1 1 1 x x x x x x x x x x x x
0 1 x 0 1 x x x x x x x x x x x x
x x x x x 0 0 1 x x x x x x x x x
x Select in g t h e u p/down cou n t er x Select in g t h e r efer en ce r egist er -A x Select in g t h e pr eloa d r egist er x "
(m ode 0) (m ode 1)
x Select in g t h e r efer en ce r egist er -B (m ode 1) 0 Select in g low byt e of t h e r egist er (defa u lt ) 1 Select in g m iddle byt e of t h e r egist er x Select in g h igh byt e of t h e r egist er x N o oper a t ion x Z ph a se in pu t is n ot effect ive (defa u lt )
x On ly n ext Z ph a se in pu t is effect ive x E ver y Z ph a se in pu t is effect ive x N o oper a t ion x LT(La t ch in g t h e cou n t va lu e) x LD(Loa din g t h e pr eloa d va lu e) x Com m a n d ID. x In h ibit
5-3. Mode 1 : Functions and formats of the command register Th e com m a n d gr ou p of Mode 1 becom es effect ive by set t in g syst em m ode in Mode 1. Th er efor e, even if t h e com m a n d gr ou p of Mode 1 is in pu t a t Mode 0, it is n ot execu t ed. Mor eover , t h e r efer en ce r egist er B ca n be a ccessed in Mode 1. Th e D0 of t h e st a t u s r egist er is m on it or t h e com pa r a t or B ou t pu t E QB. E XTA ca n be pr ogr a m m ed t o ou t pu t on e of t h r ee sign a ls (E QA, E QA+E QB, IN TE QA). E XTB ca n be pr ogr a m m ed t o ou t pu t on e of t h r ee sign a ls (E QB, IN TE QB, IN TAI). E QA It is Low on ly wh en t h e cou n t ed va lu e is equ a l t o t h e r efer en ce r egist er A va lu e. E QB It is Low on ly wh en t h e cou n t ed va lu e is equ a l t o t h e r efer en ce r egist er B va lu e. E QA+E QB It is Low wh en eit h er E QA or E QB is Low.
IN TE QA
Aft er E QA is Low, IN TE QA is h oldin g Low. It ca n be u sed for in t er r u pt r equ est . Aft er E QB is Low, IN TE QB is h oldin g Low. It ca n be u sed for in t er r u pt r equ est .
IN TE QB
IN TAI
Aft er a bn or m a l t r a n sit ion st a t e is det ect ed, IN TAI is h oldin g Low. It ca n be u sed for in t er r u pt r equ est . Th e com m a n ds of E n a ble in t er r u pt (E I), Disa ble in t er r u pt (DI) a n d r eset , a r e a va ila ble. AI r eset com m a n d r eset s t h is ou t pu t , in it ia lizes t h e ph a se discr im in a t ion cir cu it . AI r eset com m a n d is effect ive on ly wh en IN TAI is select ed (a ft er 9AH , 9BH com m a n d execu t ed).
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Format of the command register(mode 1)
D7 D6 D5 D4 D3 D2 D1 D0 H x
Oper a t ion In h ibit In h ibit
1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 1 1 1 1 0 0 0 0 1 1 1 1
1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 92 1 93
Bit descr ipt ion D7 AI Abn or m a l in pu t det ect ion fla g (on ly ph a se-sh ift ed pu lse in pu t ) It is sh own t h a t a n a bn or m a l t r a n sit ion st a t e of ph a se-sh ift ed in pu t is det ect ed. Th is fla g is clea r ed by t h e st a t u s r ea dou t . D6 Z Z/CLR in pu t m on it or It in dica t es t h e va lu e of Z/CLR t h a t is sa m pled a t t h e r isin g edge of CLK. A/U P in pu t sign a l m on it or It in dica t es t h e va lu e of A/U P sa m pled a t t h e r isin g edge of CLK. B/DN in pu t sign a l m on it or It in dica t es t h e va lu e of B/DN sa m pled a t t h e r isin g edge of CLK.
0 94 EQA+ EQB EXTA 1 95 EQA EXTA *) 0 96 In h ibit
D5 A
that
is
1 97 EQB EXTB *) 0 98 INTEQA **) D4 B
that
is
1 99 INTEQB,INTAI **) 0 9A INTAI EXTB & DI 1 9B INTAI EXTB & EI 0 9C INTEQA EXTA & DI 1 9D INTEQA EXTA & EI 0 9E INTEQB EXTB & DI 1 9F INTEQB EXTB & EI
D3 DTR Da t a r ea dy fla g of t h e r ea din g r egist er It is sh own t h a t t h e cou n t er da t a h a s been t r a n sfer ed t o t h e r ea din g r egist er by la t ch execu t ion . Th is fla g is clea r ed by r ea din g t h e da t a fr om t h e r ea din g r egist er . D2 U /D Cou n t in g dir ect ion st a t u s of in t er n a l cou n t er . A pr esen t dir ect ion wh er e a n in t er n a l cou n t er is cou n t ed is in dica t ed. (u p cou n t : "L" a n d down cou n t : "H ") D1 E QA Com pa r a t or A coin ciden t fla g I t is s h ow n t h a t t h e cou n t d a t a is cor r espon din g t o t h e da t a of r efer en ce r egist er A. D0 U U n iver sa l in pu t U m on it or ( m ode 0 ) It is possible t o do t h ou gh sign a l (U ) in pu t t o E XTB (N o.19 pin ) is dir ect ly m on it or ed.
*) default **) command reset Hx:Hexa code Note: Both EXTA and EXTB cannot be connected to other IC output, because they cannot be high- impedance in mode 1.
6. Status register Th e st a t u s r egist er is u sed t o m on it or t h ein t er n a l con dit ion . P lea se r efer t o t h e pa r a gr a ph of "4-1.CP U in t er fa ce" for t h e m et h od of r ea dou t t h is r egist er . E QB Com pa r a t or B coin ciden t fla g ( Mode 1 ) I t is s h ow n t h a t t h e cou n t d a t a is cor r espon din g t o t h e da t a of r efer en ce r egist er B.
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7.Electrical specification (1) Absolute maximum rating Ra t in g Su pply volt a ge In pu t volt a ge Ou t pu t volt a ge Oper a t ion t em per a t u r e St or a ge t em per a t u r e Symbol VDD Vi Vo Topr Tst g Va lu es -0.3 ~ 7.0 -0.3 ~ VDD+0.3 -0.3 ~ VDD+0.3 -10 ~ +70 -55 ~ +150 U n it V V V C C
(2) Recommended operating conditions P a r a m et er Su pply volt a ge Oper a t ion t em per a t u r e Symbol VDD Topr MIN . 4.75 -10 TYP . 5.0 MAX. 5.25 +70 U n it V C
(3) DC characteristics( at the recommended operating conditions ) Lim it va lu es P a r a m et er In pu t "Low" volt a ge In ou t "H igh " volt a ge Ou t pu t "Low" volt a ge Ou t pu t "H igh " volt a ge In pu t lea ka ge cu r r en t Ou t pu t lea ka ge cu r r en t St a n dby cu r r en t Oper a t ion cu r r en t Symbol VIL VIH VOL VOH I OL I OZ I DDS I DDO I OL = 4m A I OH= -2m A Vi= 0V~ VDD U n der a h igh im peda n ce Vi= 0V
or
Mea su r in g con dit ion s
MIN
U n it TYP MAX
2.0 2.4 -10 -10 -
0.8 0.4 10 10 20 40
V V V V A A A mA
VDD
f=8MH z Ou t pu t s open
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8.AC characteristics ( Ta=-10~ 70 C, Vcc=5V } 5% )
P a r a m et er C/D,CEsetup time (to D7~ D0) C/D,CE hold time (to D7~ D0) Da t a set u p t im e (t o WR -) Da t a h old t im e (t o WR - ) WR pu lse widt h C/D,CE set u p t im e (t o RD -) C/D,CE h old t im e (t o RD -) RD pu lse widt h Da t a a ccess t im e (fr om RD ) Da t a floa t dela y (fr om RD -) Clock h igh /low pu lse widt h Clock cycle t im e Reset pu lse widt h LD set u p t im e LD pu lse widt h U DC da t a defin it e dela y t im e LT set u p t im e LT pu lse widt h RDR da t a defin it e dela y t im e EXTB set time (from WR-) E XTB floa t t im e (fr om WR -) EXTA,EXTB fix time(to CLK ) A,B cycle t im e A,B h igh /low level t im e A,B ph a se differ en ce t im e Z h igh level widt h Z pu lse widt h A- set u p t im e (t o B -) (t o CLK ) (t o CLK )
Symbol t AW t WA tDW tWD tWW tAR tRA tRR tRD tDF 0 cy tRST tLDS tLDW tLDD tLTS tLTW tLTD t SEB tFEB t EXF tCYAB tPWAB t SAB t SZ t ZZ t SS t AHL tACY tUDCY tU
Con dit ion
Va lu es(U n it :n S) MIN 0 0 80 40 80 50 30 80 20 60 125 80 30 50 30 50 20 cy 4+200 cy 2+100 cy+ 50 cy+ 50 cy+ 50 cy+ 50 cy+ 50 cy 2+100 cy 2+100 cy+ 50 MAX 50 30 30 50 50 -
Syn ch r on ou s clea r m ode Asyn ch r on ou s clea r m ode Sin gle ph a se m ode Sin gle ph a se m ode Sin gle ph a se m ode U p/down m ode U p/down m ode
A h igh /low level widt h A cycle t im e U P ,DN cycle t im e U P ,DN h igh /low level widt h
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9, Timing of ZEN2011P Input timing of phase-shifted pulse signal t CYAB t PWAB A t SAB t SAB t SAB t SAB t PWAB
B t PWAB t CYAB t PWAB
Z (Syn ch r on ou s clea r m ode) t SZ t SZ
Z (Asyn ch r on ou s clea r m ode)
t ZZ
Input timing of single phase signal A t AHL t SS t ACY t AHL
B
Input timing of up/down pulse signal UP t UDCY tU DN tU tU t UDCY tU
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Write cycle C/D , CE C/D:"H igh " com m a n d wr it in g "Low" Da t a wr it in g D7 ~ D0 t AW WR t WW t DW t WD t WA
Read cycle C/D , CE C/D:"H igh " St a t u s r ea din g "Low" Da t a r ea din g RD t AR D7 ~ D0 t RD t DF t RR t RA
Clock waveform
CLK 0 0 cy
Reset waveform RE SE T t RST
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Load cycle
CLK t LDS LD t LDW t LDD Cou n t er oper a t ion U DC Old U DC in dica t es t h e con t en t of t h e u p/down cou n t er N ew (P L) (P L) St or ed va lu e in t h e pr eloa d r egist er In pu t sa m plin g
Latch cycle
CLK t LTS LT t LTW t LTD RDR RDR in dica t es t h e con t en t of t h e r ea din g r egist er (U DC) (UDC) Cou n t ed va lu e in t h e u p/down cou n t er
Output timing of EXTA or EXTB signal CLK U DC (SP -1) (SP ) (SP +1)
E XTA or E XTB (SP ) St or ed va lu e in t h e r efer en ce r egist er WR H i -Z E XTB
t EXF
H i -Z Va lid t SEB a t t h e execu t in g com m a n d '91H ' t FEB a t t h e execu t in g com m a n d '90H ' ZENIC - 14 Inc.
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ZEN2011P
10. Outline of software design Th e ZEN2011P is con t r olled by soft wa r e. F ollowin g is t h e ou t lin e of design in g soft wa r e, in a for m of flow ch a r t , for t h e ba sic oper a t ion s. (1) System mode set St a r t Wr it e com m a n d wor d in t o t h e com m a n d r egist er 90H = m ode 0 (defa u lt ) 91H = m ode 1 End (2) Initial value set to the each register St a r t Wr it e com m a n d wor d in t o t h e com m a n d r egist er a ccess poin t er set Wr it e da t a 3 t im es ever y 8 bit End (3) Command writes St a r t Wr it e com m a n d wor d in t o t h e com m a n d r egist er End (4) Count data read St a r t Wr it e com m a n d wor d in t o t h e com m a n d r egist er a ccess poin t er set Rea d da t a 3 t im es ever y 8 bit End (5) Status read St a r t Rea d da t a fr om t h e st a t u s r egist er End
C/D = "H " CE = "L" WR = "L"
C/D = "H " CE = "L" WR = "L"
C/D = "H " CE = "L" WR = "L" C/D = "L" CE = "L" WR = "L"
C/D = "H " CE = "L" WR = "L"
C/D = "H " CE = "L" WR = "L" C/D = "L" CE = "L" WR = "L"
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11. Interface example Z80
Z80CPU
ADDRESS DECODER
ZEN2011P CE A/ UP B/ DN Z/ CLR U SEL2 ` SEL0 UD/ AB DI R W R LD LT EQ
A7 ` A1
A0 RD
C/ D RD
W R I ORQ D7 ` D0
D7 ` D0
VDD VSS RESET
6809
68B09CPU A15 ` A9 Q E
ADDRESS DECODER
ZEN2011P CE A/ UP B/ DN Z/ CLR U SEL2 ` SEL0 UD/ AB DI R W R LD LT EQ
RD R/ W
D7 ` D0
D7 ` D0
VDD VSS RESET
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8086(Minimum mode)
8086CPU MM N/ X CLK READY RESET MIO / RD VDD
W R DT/ R DEN ALE GND AD0 ` AD15 A16 ` A19 BHE STB OE B8282 Lat c h ( 2or 3) A0 ADDRESS DECODER
ZEN2011P CE A/ UP B/ DN Z/ CLR U SEL2 ` SEL0 UD/ AB DI R W R T OE B8286 Tr anscei ver ( 2) LD LT EQ
C/ D RD
D7 ` D0
12. Package Outlines ( Dimensions in mm )
1
28
36. 0 } 0. 3
14
15 0. 51M N I 4. 25 } 0. 25 13. 2 } 0. 25 3. 25 } 0. 25
0. 25 } 0. 05 0 ` 15 K
15. 24TYP.
P- 2. 54TYP.
0. 5 } 0. 1
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ZENIC r eser ves t h e r igh t t o m a ke ch a n ges in it s pr odu ct wit h ou t a n y n ot ice t o im pr ove r elia bilit y, fu n ct ion or design . ZENIC does n ot a ssu m e a n y lia bilit y a r isin g ou t of t h e a pplica t ion or u se of a n y pr odu ct or cir cu it descr ibed h er ein ;n eit h er does it con vey a n y licen se u n der it s pa t en t r igh t s n or t h e r igh t s of ot h er s. In for m a t ion con t a in ed in t h is pu blica t ion r ega r din g device a pplica t ion s a n d t h e like is in t en ded t h r ou gh su ggest ion on ly a n d m a y be su per seded by u pda t es. ZENIC pr odu ct s a r e n ot design ed, in t en ded, or a u t h r ized for u se a s com pon en t s in syst em s in t en ded for su r gica l im pla n t in t o t h e body, or ot h er a pplica t ion s in t en ded t o su ppor t or su st a in life, or for a n y ot h er a pplica t ion in wh ich t h e fa ilu r e of t h e ZE N IC pr odu ct s cou ld cr ea t e a sit u a t ion wh er e per son a l in ju r y or dea t h m a y occu r . Z80 is a r egist er ed t r a dem a r k of Zilog Inc. 6809 is a r egist er ed t r a dem a r k of Motorola Inc. 8086 is a r egist er ed t r a dem a r k of Intel Corp. All r igh t r eser ved. Copyr igh t 1991, ZENIC INC.
ZENIC Inc.
U RL h t t p://www.zen ic.co.jp/ 1-17-14, Oh ga ya Oh t su Sh iga 520-2144, J AP AN F a x. +81-77-543-9431 E -m a il su ppor t @zen ic.co.jp ZENIC Inc. - 18 -

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